Memory with row-wise write and column-wise read

ABSTRACT

A memory is organized into both rows and columns, and includes a write access circuit connected to the memory cells in a row-wise manner and a read access circuit connected to the memory cells in column-wise manner.

FIELD OF THE INVENTION

[0001] The present invention relates to a memory; more specifically to arandom access memory (RAM) where data may be written to the RAM in arow-wise manner and data may be read from the RAM in a column-wisemanner.

BACKGROUND OF THE INVENTION

[0002] Certain data processing applications are both memory intensive,requiring multiple read and write cycles to and from a memory, andrequire the interleaving of data. For example, Forward Error Correction(FEC) schemes are used to increase a transceiver's error correctioncapabilities Data is interleaved, transmitted, received, andde-interleaved. De-interleaving involves interleaving previouslyinterleaved data, and thus is effectively the same process asinterleaving. Other data processing tasks may use interleaving, and mayuse techniques requiring data to be written in one dimension, such as arow, and read in another dimension, such as a column.

[0003] In one method of interleaving data, data is written row-wise intorows having a certain number of columns, and then is read column-wise.For example, FIG. 1 is an example of a table illustrating theorganization of bits during interleaving. Table 500 includes m*n bits502 arranged in m rows 510 and n columns 520. The data to be interleavedis written into the table 500 as bits 502 row by row. Each bit 502 isthen read from the table 500 column by column. In a digital dataprocessing system a memory such as a RAM is used to store such datawhile interleaving.

[0004] A typical known memory, such as a RAM, organizes data as bits orbytes arranged in sets of rows. Such a memory allows access to data inone manner only—for example, by reading and writing blocks of data, eachblock comprising an entire row, or by reading and writing blocks of datawithin a row. A series of bits may be efficiently written into a memoryhaving such a structure in a row-wise manner, as the memory allowsaccess to data in units of rows (or as units of blocks forming theserows). A single write operation may suffice to fill an entire row. Toread the same data in a column-wise manner requires sequentiallyaccessing each row; one bit or unit of data is read for each row. Foreach column desired to be read, the number of sequential read operationsor read cycles is equal to the number of rows Thus, much more time andpower is consumed during the read operation than during the writeoperation.

[0005] Such memories typically include address decoding circuitry foraccess to the proper portion of the memory for reading or writing. Anaddress decoder may, for example, accept an address of a bit or byte tobe accessed. The address decoder determines in which row the byte isstored, and signals that row for a read or write operation. Certain“dual port” memories include two address decoders. Such memories mayallow simultaneous read and write operations; however, such memoriesallow simultaneous read and write operations in the same dimension only;i.e., reading to and writing from the memory in a row-wise manner only.

[0006] A sequence in a memory or a table of data is termed a “row” or a“column” based on the visual orientation when presented to a humanbeing. Since, when stored in a memory device, “rows” and “columns” arearbitrary designations, when used herein with respect to a specificdevice or applications the terms row and column may be transposed. Forexample, in the table of FIG. 1, if the table 500 is rotated 90 degrees,each row 510 may be termed a column, and each column 520 may be termed arow. While a row may also be termed a line, when used herein, the termline is restricted to its common usage as a device (such as a wire or alayer of electrically transmitting material) which transmits signals.However, using another sense of the word “line,” a set of data writtenrow-wise can also be said to be written line-wise.

[0007] Certain data processing tasks that require interleaving, such asFEC, require data to be read in a dimension opposite the dimension itwas written. Conventional memory devices perform this taskinefficiently.

[0008] Thus, a need exists for a memory device that allows quickeraccess to data, in particular data organized and accessed both by rowand by column.

SUMMARY OF THE INVENTION

[0009] One embodiment of the present invention provides a memory whichis organized into both rows and columns, and which includes a writeaccess circuit connected to the memory cells in a row-wise manner and aread access circuit connected to the memory cells in column-wise manner.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present invention will be understood and appreciated morefully from the following detailed description taken in conjunction withthe drawings in which:

[0011]FIG. 1 is an example of a table illustrating the organization ofbits during interleaving;

[0012]FIG. 2 is a schematic diagram of a memory device according to anembodiment of the present invention; and

[0013]FIG. 3 is a block diagram depicting a data processing deviceincluding a memory according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0014] In the following description, various aspects of the presentinvention will be described For purposes of explanation, specificconfigurations and details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will also beapparent to one skilled in the art that the present invention may bepracticed without the specific details presented herein. Furthermore,well known features may be omitted or simplified in order not to obscurethe present invention.

[0015] An exemplary embodiment of the present invention provides for amemory device which may accept data for write operations in a row-wisemanner and which may output data in read operations in a column-wisemanner. In such a manner, data may quickly be written in a row-wisemanner and quickly read in a column-wise manner. Thus the presentinvention is suited to applications which require interleaving of dataand thus which require quick access of data in both a row andcolumn-wise manner.

[0016]FIG. 2 is a schematic diagram of a memory device according to anembodiment of the present invention. Referring to FIG. 2, memory 1includes a plurality of memory units 10, each storing one bit of data.The memory units 10 are divided into rows 2 and columns 4. Memory 1includes row address decoder 20, for accessing individual rows 2 ofdata, column address decoder 30, for accessing individual columns 4 ofdata, a set of write lines 24, for writing data to the memory units 10,and a set of read lines 34, for reading data to the memory units 10.Each write line 24 is connected to a set of memory units 10 comprising arow 2, and each read line 34 is connected to a set of memory units 10comprising a column 4. In operation, data is written to memory units 10via the write lines 24, and data is read from the memory units 10 viathe read lines 34.

[0017] Each memory unit 10 is preferably a bi-stable SRAM memory cell ofknown CMOS construction, storing one bit of data and includingcomponents such as transistors and inverters. In alternate embodimentsother types of memory units having other construction may be used; suchmemory units are well known in the art. For example, a memory unit maystore more than one bit of data. Preferably, each of the row addressdecoder 20 and column address decoder 30 are address decoders of knownconstruction. In alternate embodiments the write access circuit and readaccess circuit used to read and write data to and from memory cells maybe of different construction and may include other functions; suchaccess circuits are well known in the art. In an exemplary embodimentthe memory unit 1 fits on one chip, and further may be combined on onechip with other components such as a processor.

[0018] Extending from the row address decoder 20 is a set of row addresslines 22, for selecting individual rows 2 of memory units 10 for datawriting; each row address line 22 is connected to a set of memory units10 comprising a row 2.

[0019] Extending from the column address decoder 30 is a set of columnaddress lines 32, for selecting individual columns 4 of memory units 10for data reading; each column address line 32 is connected to a set ofmemory units 10 comprising a column 4.

[0020] The inputs to the row address decoder 20 and column addressdecoder 32 may be varied, and may be presented to other units in acomputing system in different manners. For example, the memory 1 mayhave as interfaces to other units a set of row address lines and a setof column address lines, and in addition control lines such as aread/write command line and a set of data lines. The memory 1 may beplaced in a package which provides a row-wise write/column-wise readmemory, or may be integrated into a device to provide a row-wisewrite/column-wise read memory. The write lines 24 and read lines 34 maybe connected, directly or indirectly, to the interface or output forsuch a row-wise write/column-wise read memory. Other methods ofinterfacing the memory 1 with other units may be used; such interfacesare well known in the art.

[0021] In operation, data is written to the memory 1 one row at a time.An address signal is sent to the row address decoder 20 via knownmethods, and the row address 20 decoder decodes the signal, sending awrite signal to the one of the row address lines 22 corresponding to therow 2 addressed by the address signal. An address signal may be, forexample, a set of bits corresponding to an address which may be decodedinto an address corresponding to on of the row address lines 22. Methodsof converting memory address signals into signals on memory addresslines are known. At the same time, the data to be written to the memoryunits 10 comprising the selected row 2 appears on the write lines 24,and the memory units 10 comprising the selected row accept the data.

[0022] To read a column, an address signal is sent to the column addressdecoder 30 via known methods, and the column address 30 decoder decodesthe signal, sending a read signal to the one of the column address lines32 corresponding to the column 4 addressed by the address signal. Thedata to be read from the memory units 10 comprising the selected column4 appears on the read lines 44, and the interface (not shown) providesthe data to a unit accepting the data (not shown).

[0023] Preferably, during operation, when a row 2 is written, the entirerow 2 is written and when a column 4 is read, the entire column 4 isread. In alternate embodiments, data may be written or read in blockssuch as bytes which may be of a smaller dimension than a row or column.Further, since a “row” and a “column” is an arbitrary designation, amemory according to an embodiment of the present invention may be writeenabled by column and read enabled by row. In alternate embodiments,each of the dimensions need not be restricted to only reading or onlywriting; for example, the rows, columns, or both may be both read andwrite enabled.

[0024] While, as depicted, memory 1 is a two by two square, the memoryaccording to the present invention may include any dimensions and neednot be square. For example, the rows may be of different dimension thanthe columns. Preferably, the dimensions of the memory 1 are chosen basedon the application using the memory 1. Furthermore, the memory cellsneed not be divided into “rows” and “columns”; the memory units may bedivided into any dimensions, where different sets of memory units areplaced in each dimension.

[0025] Various applications may be used with a memory according toembodiments of the present invention. FIG. 3 is a block diagramdepicting a data processing device including a memory according to anembodiment of the present invention. Such a data processing device 100(such as a personal computer or a specialized card or subsystem in acomputer) which performs, for example, FEC, may include a memory 110according to an embodiment of the present invention, a processor 120(such as a microprocessor), a random access memory 150 (such as an SRAMor DRAM) and a code memory 130 (such as an RAM or ROM) storinginstructions. The components may be connected by a data bus 140, whichmay be a series of data busses. Other known components (not shown) maybe included, such as a power supply, an input output controller.

[0026] To perform a data interleaving application, the processor 100,following instructions contained in code memory 130, may accept a blockof data. The data may be written to the memory 110 in a row-wisefashion, row by row. The data may be then read from the memory 110 in acolumn-wise fashion, column by column, processed by the processor 120,and transmitted. In one embodiment, each of the components of the dataprocessing device 100 are placed on one chip. Other applications andsystems may use a memory according to the present invention.

[0027] It will be appreciated by persons skilled in the art that thepresent invention is not limited by what has been particularly shown anddescribed hereinabove. Rather the scope of the invention is defined bythe claims that follow:

What is claimed is:
 1. A memory comprising: a plurality of memory units,the plurality of memory units being organized into rows, each rowincluding a subset of memory units, the plurality of memory units alsobeing organized into columns, each column including at least one memoryunit from each of the rows; a write access circuit connected to sets ofthe memory units in a row-wise manner and a read access circuitconnected to sets of the memory units in column-wise manner.
 2. Thememory of claim 1, wherein the read access circuit allows all the memoryunits from a selected one of the columns to be read simultaneously. 3.The memory of claim 1, wherein the write access circuit allows all thememory units from a selected one of the rows to be written tosimultaneously.
 4. The memory of claim 1, wherein: the write accesscircuit includes at least an address decoder; and the read accesscircuit includes at least an address decoder.
 5. The memory of claim 1,wherein the write access circuit includes read access circuitry.
 6. Thememory of claim 1, wherein the read access circuit includes write accesscircuitry.
 7. The memory of claim 1, wherein: the write access circuitincludes at least a set of write address lines, each write address lineattached to a set of memory units; and the read access circuit includesat least a set of read address lines, each read address line attached toa set of memory units.
 8. The memory of claim 7, wherein: in each row,each memory unit in that row is attached to a different read addressline; and in each row, each memory unit in that row is attached to thesame write address line.
 9. The memory of claim 1, wherein the memoryincludes a random access memory.
 10. The memory of claim 1, wherein eachmemory unit stores one bit.
 11. A memory comprising: a plurality ofmemory units, the plurality of memory units being organized into rows,each row including a subset of memory units, the plurality of memoryunits also being organized into columns, each column including at leastone memory unit from each of the rows; a write access circuit connectedto sets of the memory units in a row-wise manner, wherein the writeaccess circuit allows all the memory units from a selected one of therows to be written to simultaneously; and a read access circuitconnected to sets of the memory units in column-wise manner.
 12. Amemory comprising: a plurality of memory units, the plurality of memoryunits being organized into rows, each row including a subset of memoryunits, the plurality of memory units also being organized into columns,each column including at least one memory unit from each of the rows; awrite access circuit including at least an address decoder and connectedto sets of the memory units in a row-wise manner; and a read accesscircuit including at least an address decoder and connected to sets ofthe memory units in column-wise manner.
 13. A memory comprising: aplurality of memory units; a write access circuit, the write accesscircuit including a set of write control lines, each write control linebeing connected to a row-wise set of memory units; and a read accesscircuit, the read access circuit including a set of write control lines,each read control line being connected to a column-wise set of memoryunits, each column-wise set of memory units including one memory unitfrom each row-wise set of memory units.
 14. A memory comprising: aplurality of memory units, the plurality of memory units being organizedinto rows, each row including a subset of memory units, the plurality ofmemory units also being organized into columns, each column including atleast one memory unit from each of the rows; a write access circuitconnected to sets of the memory units in a row-wise manner, the writeaccess circuit including at least a set of write address lines, eachwrite address line attached to a set of memory units; and a read accesscircuit connected to sets of the memory units in column-wise manner, theread access circuit including at least a set of read address lines, eachread address line attached to a set of memory units.
 15. A memorycomprising: a plurality of memory units, the plurality of memory unitsbeing organized into rows and columns; a write access circuit connectedto sets of the memory units in a row-wise manner, the write accesscircuit including at least an address decoder and a set of write addresslines, each write address line attached to a set of memory units; and aread access circuit connected to sets of the memory units in column-wisemanner, the read access circuit including at least a an address decoderand a set of read address lines, each read address line attached to aset of memory units.
 16. A memory comprising: a plurality of memoryunits, the plurality of memory units being organized into a first set ofsets of memory units according to a first dimension and a second set ofsets of memory units according to a second dimension; a write accesscircuit allowing a set of data to be written to a set of memory units ina selected set from the first set of sets; and a read access circuitallowing a set of data to be read from a set of memory units in aselected set from the set of second sets.
 17. The memory according toclaim 16, wherein the first dimension corresponds to rows and the seconddimension corresponds to columns.
 18. The memory of claim 16, whereinthe write access circuit allows all the memory units from a selected setfrom the first set of sets to be written to simultaneously.
 19. Thememory of claim 16, wherein: the write access circuit includes at leastan address decoder; and the read access circuit includes at least anaddress decoder.
 20. The memory of claim 16, wherein: the write accesscircuit includes at least a set of write address lines, each writeaddress line being attached to a set of memory units; and the readaccess circuit includes at least a set of read address lines, each readaddress line being attached to a set of memory units.
 21. A memorycomprising: a plurality of memory units, the plurality of memory unitsbeing organized into a first set of sets of memory units according to arows and a second set of sets of memory units according to columns; awrite access circuit allowing a set of data to be written to a set ofmemory units in a selected set from the first set of sets; and a readaccess circuit allowing a set of data to be read from a set of memoryunits in a selected set from the set of second sets.
 22. A memorycomprising: a plurality of memory units; a write access means, the writeaccess means including a set of write control lines, each write controlline being connected to a row-wise set of memory units; and a readaccess means, the read access means including a set of write controllines, each read control line being connected to a column-wise set ofmemory units, each column-wise set of memory units including one memoryunit from each row-wise set of memory units.
 23. A memory comprising: aplurality of memory units, the plurality of memory units being organizedinto a first set of sets of memory units according to a first dimensionand a second set of sets of memory units according to a seconddimension; a write access circuit including at least an address decoderand allowing a set of data to be written to a set of memory units in aselected set from the first set of sets; and a read access circuitincluding at least an address decoder and allowing a set of data to beread from a set of memory units in a selected set from the set of secondsets.
 24. A memory comprising: a plurality of memory units, theplurality of memory units being organized into a first set of sets ofmemory units according to a first dimension and a second set of sets ofmemory units according to a second dimension; a write access circuitincluding at least a set of write address lines, each write address linebeing attached to a set of memory units; and a read access circuitincluding at least a set of read address lines, each read address linebeing attached to a set of memory units.
 25. A memory comprising: aplurality of memory units means, the plurality of memory unit meansbeing organized into rows, the plurality of memory unit means also beingorganized into columns; a write access means allowing a set of data tobe written to set of memory unit means in a selected one of the rows;and a read access means allowing a set of data to be read from a set ofmemory unit means in a selected one of the columns.
 26. A memorycomprising: a plurality of memory units, the plurality of memory unitsbeing organized into rows, the plurality of memory units also beingorganized into columns; a write access means allowing a set of data tobe written to set of memory unit means in a selected one of the rows;and a read access means allowing a set of data to be read from a set ofmemory unit means in a selected one of the columns.
 27. The memory ofclaim 26, wherein: the write access means includes at least an addressdecoder means; and the read access means includes at least an addressdecoder means.
 28. The memory of claim 26, wherein: the write accessmeans includes at least a set of write address lines, each write addressline being attached to a set of memory units; and the read access meansincludes at least a set of read address lines, each read address linebeing attached to a set of memory units.
 29. A data processing systemcomprising: an SRAM; and a second memory according to claim
 1. 30. Adata processing system according to claim 29 comprising a dataprocessor.
 31. The data processing system of claim 29, wherein the dataprocessor and second memory are disposed on the same chip.
 32. The dataprocessing system of claim 29, wherein: the write access circuitincludes at least a set of write address lines, each write address lineattached to a set of memory units; and the read access circuit includesat least a set of read address lines, each read address line attached toa set of memory units.
 33. A data processing system comprising: a memoryaccording to claim 1; and a data processor, wherein the memory and dataprocessor are disposed on the same chip.
 34. The data processing systemof claim 33, wherein: the write access circuit includes at least a setof write address lines, each write address line attached to a set ofmemory units; and the read access circuit includes at least a set ofread address lines, each read address line attached to a set of memoryunits.